Phase-switching dual modulus prescaler

ABSTRACT

A phase-switching dual modulus prescaler having a dual modulus divider is provided. Said divider comprises a first and second divide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B) is coupled to the output of said first divide-by-2 circuit (A) and at least said second divide-by-two circuit (B) comprises a four phase output each separated by 90°. A phase selection unit (PSU) is provided for selecting one of the four phase outputs (I p, I   n , Q p , Q n ; INi, INni, INq, Innq) of the second divide-by-2 circuit (B). Moreover, a phase control unit is provided for providing control signal (C 1 , NC 0 ; C 2 , NC 2 ; C 3 , NC 3 ) to the phase selection unit, wherein the phase selection unit (PSU) performs the selection of the four phase outputs (I p , I n , Q p , Q n ; INi, INni, INq, Innq) according to the control signals (C 0 , NC 0 ; C 1 , NC 1 ; C 2 , NC 2 ). Said phase selection unit (PSU) is implemented based on direct logic. The implementation of the phase selection unit based on direct logic enables a higher speed and saves area on the chip.

The invention relates to a phase-switching dual modulus prescaler, and afrequency synthesizer.

The phase-locked loop (PLL) method of frequency synthesize is the mostcommonly used method for producing high frequency oscillations in moderncommunication equipment. A programmable frequency synthesizer is adevice which is capable of generating a signal having a frequencyselected from within a range of frequencies. A programmable frequencysynthesizer utilizes a digital phase-locked loop circuit using a voltagecontrolled oscillator VCO to generate an output signal. The PLLcomprises a feedback and control loop monitoring the frequency of thesynthesizer output signal, compares its frequency to that of a referencesignal and controls the VCO to adjust the frequency of the synthesizeroutput signal. The output signal of the VCO is most often divided by adigital frequency divider, also called a prescaler, in the feedbackportion of the loop, so that a feedback signal comprises a frequencywhich is a selected sub-multiple of a output signal of a synthesizer. Incase of an integer-N divider, the divider produces an output signal forevery n-th input pulse so that the input frequency is divided by n. Thephase of the feedback signal is compared to that of a stable referencesignal and the difference thereof defines an error signal which isfeedback to the VCO. The VCO adjusts the frequency of the synthesizer inorder to reduce the error signal. Usually, the reference signal has alower frequency than the output signal of the synthesizer.

The frequency selection capabilities of the output signal of thesynthesizer is determined by the programmability of the frequencydivider dividing the output signal of the synthesizer by a selecteddivider number. This selected divider number is chosen to equal thedesired frequency of the synthesizer output signal divided by thefrequency of the reference signal. Therefore, selecting a differentdivider number results in the change of the frequency of the outputsignal of the synthesizer.

The two blocks of a frequency synthesizer that are working at the fullfrequency are the VCO and the prescaler. As mentioned above theprescaler divides the output frequency of the VCO by a certain ratio inorder to get a low frequency signal. This signal is then locked by thePLL onto a stable reference frequency. In order to achieve a betterfrequency resolution the division ratio is typically a variable in formof N/N+1, i.e. this divider is called dual-modulus prescaler. Theprogrammable prescaler is a N-fixed prescaler with a pulse swallowcircuit realizing a N+1 division. By changing the value of N in smallinteger-steps the output frequency of the VCO is controlled.

In order to achieve a suitable synthesizer for high frequency a largedivider ratio using high speed logic is required. However, such largedivider would be very expensive because of the required large chip size.Furthermore, such a large loop divider would draw a very large currentso that it is not suitable for mobile of portable applications.

A conventional high speed dual modulus prescaler comprises asynchronized divider and sometimes an asynchronized divider for largedivision numbers, however such high speed synchronized dual modulusdividers require a lot of power consumption.

J. Craninckx proposed in his Ph. D. thesis at the KU Leuven a concept ofphase-switching dual modulus prescaler. Two divide-by-2 dividers areused together with a phase select unit in order to implement a 4/5division. A subsequent additional 128-divider is used to generate adivision number of 512. This concept may be applied for example for IEEE802.11a. The operational frequency is from 5.15 GHz to 5.35 GHz for theUNII band and the channel spacing is 20 MHz In the case of zero-IF (ZIF)architecture, a reference frequency of 20 Mz is usually enough but fornear-ZIF a reference frequency of 10 MHz is often chosen. Theabove-mentioned circuit furthermore comprises a modulus control unitwith a five bits control signal enabling it to swallow up to 32 pulsessuch that any ratio between 512 and 544 can be achieved. Accordingly, aninteger-N prescaler architecture is provided with a division ratiobetween 515 to 535.

If a reference frequency of 10 MHz is applied to the above circuit, then10 MHz×516 equals to 5.16 GHz, which constitutes the center to the firstchannel from 5.15 GHz to 5.17 GHz with a channel width of 20 MHz. Thenext channel is then 20 MHz of from the center of the first channel,i.e. 5.17 GHz to 5.19 GHz with a center at 5.18 GHz. This center can beobtained by a division ratio of 518 with a reference frequency of 10 MHzThe last or maximum channel is from 5.33 GHz to 5.35 GHz, which can beachieved by a division ratio of 534.

However, since up to 128 division signals are to be generated from thephase select signal, this will effect the speed of this circuit.

An example of a modified phase-switching dual-modulus prescaler is shownin “CMOS divide-by- 8/9 for frequency synthesizer”, by Kan Kwok Kei,Toby at the department of electrical and electronic engineering, HKUST,26.04.1999. Such a prescaler consists of a first high frequencydivide-by-2-circuit operating at full speed of the input frequency. Thefirst divide-by-2-circuit is followed by a second divide-by-2-circuitwhich has four phase output signals each differing 90° in phase fromeach other. A phase selection circuit selects one of the four phaseoutput signal of the second divide-by-2-circuit The phase select circuitcomprises two switchable amplifiers and three NAND gates. In theswitchable amplifiers the In-phase (I) and the quadrature (Q) signalsare amplified and according to controls signals C1, C2 the positive orthe negative amplification of the input signals are chosen. The speed ofthe switchable amplifiers constitute the limiting factor of the maximumspeed of this prescaler. The phase selection circuit basicallyimplements a multiplexer, i.e. one of the four phase output signals ofthe second divide-by-2circuit is selected as output thereof. Accordingto a third control signal CO one of the outputs of the two switchableamplifiers are chosen as output. The control signals are changed atevery positive edge of the final output realizing a 90° delay withrespect to the present signal. Since the phase selection circuit isproceeded by two divide-by-2 circuits the 90° delay is actuallycorresponding to a period of the input signal of the prescaler when aN+1 division ratio is to be implemented.

With this circuit a working speed of 1.85 GHz is realized. However, forapplication like wireless data networking higher operation frequenciesare needed.

In “A 5.3 GHz Programmable Divider for HiPerLAN in 0.25 μ CMOS”, byKrishnapura et al. IEEE Journal of Solid State Circuits, vol. 35, no. 7,pp. 1019 to, 1024, July 2000, a frequency divider based on a operationfrequency of 5.3 GHz is shown. The frequency divider is employing phaseswitching and comprises a first divide-by-2 circuit and a seconddivide-by-2 circuit with four phase output signals. The output signalsof the second divide-by-2 circuit are input to a retiming circuit whichswitches from one of these four output signals to another one accordingto control signals from a decoder. The four output signals of the seconddivide-by-2 circuit are separated by 90° from each other. At any giventime, only one of these outputs are connected to a subsequent dividerthrough a multiplexer. The swallowing of a cycle and thereby augmentingthe total count of the frequency divider by 1 is achieved by switchingto an output of the second divide-by-2 circuit that is lagging thecurrent signal by 90°. In order to achieve an arbitory division factorthe input cycles can be swallowed by changing the control inputs of themultiplexer appropriately. In the absence of phase switching the dividercomprises a division factor of 4×N. However, if the phases are switchedK times in each cycle of the output of the divider, K input cycles areswallowed and the division factor is augmented by K. By varying K aprogrammable frequency divider can be achieved. A pulse generatorgenerates K pulses per output cycle, wherein K is set by the programminginputs of the pulse generator. A divide-by-4 counter is used as inputsignal of the decoder which is controlling the multiplexer. Thisdivide-by-4 counter is clocked by the output pulses of the pulsegenerator and cycles through four states, each corresponding to one ofthe four possible connections in the multiplexer. In order to provide aglitch-free switching, the switching must be performed when the 0° andthe 90° output of the second divide-by-2 circuit are both high.Furthermore, in order to assure that the clock signals as well as thecontrol signals arrive synchronously at the inputs of the multiplexer abuffer is implemented in the clock line with a delay that is the same asthat of the control signal generator, in order to correct timinginaccuracies.

It is therefore an object of the present invention to provide animproved high speed prescaler.

This object is solved by a phase-switching dual modulus prescaleraccording to claim 1, and a frequency synthesizer according to claim 8.

Therefore, a phase-switching dual modulus prescaler having a dualmodulus divider is provided. Said divider comprises a first and seconddivide-by-2 circuit (A;B), wherein said second divide-by-2 circuit (B)is coupled to the output of said first divide-by-2 circuit (A) and atleast said second divide-by-2 circuit (B) comprises a four phase outputeach separated by 90°. A phase selection unit (PSU) is provided forselecting one of the four phase outputs I_(p), I_(n), Q_(p), Q_(n); INi,INni, INq, INnq of the second divide-by-2 circuit (B). Moreover, a phasecontrol unit is provided for providing control signals (C0, NC0; C1,NC1; C2, NC2) to the phase selection unit, wherein the phase selectionunit PSU performs the selection of the four phase outputs I_(p), I_(n),Q_(p), Q_(n); INi, INni, INq, INnq according to the control signals C0,NC0; C1, NC1; C2, NC2. Said phase selection unit (PSU) is implementedbased on direct logic.

The implementation of the phase selection unit based on direct logicenables a higher speed as compared to implementations with switchableamplifiers and saves area on the chip.

According to an aspect of the invention, the output OUT of the phaseselection unit PSU is implemented according to the following logic code:OUT= NC0•NC1•INi + NC0•C1•INni + C0•NC2•INnq + C0•C2•INq ,wherein +, •, represent an OR-, AND, and NAND functions, respectively.By this arrangement a proper signal representation of the controlsignals C0, C1, C2 out of the output signals of the divider is madepossible.

According to a further aspect of the invention a divide-by-4 circuit UAis provided being coupled to the output of the phase selection unit PSU.Said divide-by-4 circuit UA comprises a sixth and seventh divide-by-2circuit F, G each with a four phase output I_(p), I_(n), Q_(p), Q_(n)separated by 90°. Said seventh divide-by-2 circuit G is coupled to thequadrature output Qp, Q of the sixth divide-by-2 circuit F.

According to still a further aspect of the invention, said phase controlunit (RTU) comprises a fourth and fifth divide-by-2 circuit D, E eachwith a four phase output I_(p), I_(n), Q_(p), Q_(n) separated by 90°.Said fourth and fifth divide-by-2 circuit D, E are coupled in series.The In-phase output I_(p), I_(n) of the fifth divide-by-2 circuit Ecorresponds to the control signal C0. The In-phase output I_(p), I_(n)of the fourth divide-by-2 circuit D corresponds to the control signalC1. The quadrature phase output Q_(p), Q_(n) of the fourth divide-by-2circuit E corresponds to the control signal C2.

According to still a further aspect of the invention said phase controlunit RTU further comprises a D-latch DL coupled to the input of thefifth divide-by-2 circuit E. Said D-latch DL receives the previous stateof the In-phase output Ip, I_(n) of the seventh divide-by-2 circuit Gand a signal ‘modul’ indicating the number of phase switching as inputsignals.

According to a preferred aspect of the invention, said prescaler furthercomprises a synchronization loop coupled to the dual modulus divider 10for reclocking the dual modulus divider 10.

The invention as well as the embodiments thereof will now be describedin more detail with reference to the drawings, in with:

FIG. 1 shows a block diagram of a receiver,

FIG. 2 shows a block diagram of a programmable prescaler PS of FIG. 1according to the invention,

FIG. 3 shows a 16/17 divider of FIG. 2, according to the invention,

FIG. 4 shows a circuit diagram of the phase selection unit of FIG. 3,according to the invention,

FIG. 5 shows a retiming unit and a phase selection unit of FIG. 4,according to the invention, and

FIG. 6 shows a timing diagram of the divider, according to theinvention.

FIG. 1 shows a block diagram of a receiver which can be used in the IEE802.11a standard. The upper part of FIG. 1 shows an antenna ANTconnected to a low noise amplifier LNA, which is connected to a firstand second mixer MI, MQ, which are in turn connected to ananalog-digital converter ADC. The lower part of FIG. 1 shows animplementation of a PLL-circuit. The PLL circuit comprises a voltagecontrolled oscillator VCO, a first divide-by-2 circuit, a prescaler PS,a phase frequency detector PFD, a reference crystal Xtal, a charge pumpCP and a low pass filter LPF. The output of the divide-by-two circuit iscoupled to the first and second mixer MI, MQ.

In the following the prescaler PS will be described in more detail.

FIG. 2 shows a block diagram of the prescaler of FIG. 1. Theprogrammable prescaler comprises a 16/17 divider 10, a buffer 20, adivider 30, a decision unit 40, a synchronizing unit 50, and aD-flip-flop 60. The 16/17 divider 10 is connected to the buffer 20,which in turn is connected to the divider 30. The divider 30 has fiveoutput signals, namely /2, /4, /8, /16 and /32 and a zero detectionoutput ‘zero’. These five output signals are input to the decision unit40 and the synchronizing unit 50. The decision unit 40 furthermorereceives a 5 bit control signal b0, b1, b2, b3 and b4 and the output ofthe decision unit 40 forms an input to the synchronizing unit 50. Theoutput of the synchronizing unit 50 is input to the clock input of theD-flip-flop 60. The input ‘data’ thereof is connected to the supplyvoltage VDD. The output signal ‘zero’ of divider 30 is connected to theCD input of the D-flip-flop 60. The output signal of the D-flip-flop 60is feedback to the 16/17 divider 10 and input to its ‘reclock’ input.

The divider 30 generates the signals /2, /4, /8, /16 and /32, which areinput to the decision unit 40. These signals are used to generate asignal which indicates how many pulses should be swallowed, 1, 2, . . ., 32. This is performed on the basis of the 5 bit control signal b0, b1,b2, b3 and b4.

The swallowing of one pulse is performed by delaying one or more pulses,i.e. a frequency division is performed related to your input signal. Theswallowing of one pulse is identical to a divide-by-2.

If the synchronizing unit detects, e.g. 11111, then the clock input ofthe D-flip-flop 60 is enabled and the 16/17 divider 10 is reclocked, ifa 0 is detected at the ‘zero’ output of the divider 30. Thereby asynchronization pulse is implemented, in order to reclock the circuitand to remove delays due to latches. Accordingly, a programmableprescaler is realized which is able to divide the input signal by anyinteger between 512 and 544, since 16*32=512 and up to 32 pulses can beswallowed, resulting in 512+32=544.

FIG. 3 shows a block diagram of the 16/17 divider 10 of FIG. 2. Thedivider 10 comprises a first and second divide-by-2 circuit A, B. Thesecond divide-by-2 circuit B is connected with its inputs to theIn-phase outputs Ip, In of the first divide-by-2 circuit A. A thirddivide-by-2 circuit C is connected to the quadrature output Qp, Q_(n) ofthe first divide-by-2 circuit A, and its outputs Ip, In, Qp, Q_(n) areconnected to a load Ld. Additionally, the divider 10 comprises a phaseselection unit PSU, a retiming unit RTU and a divide-by-four unit UA.The retiming unit RTU generates three control signals C0, C1, C2 forcontrolling the phase switching in the phase selection unit PSU. Thefour phase output signals of the second divide-by-2 circuit B are inputto the phase selection unit PSU. According to the control signals C0,C1, C2 provided by the retiming unit RTU, the phase selection unit PSUselects one of the four phase output signals of the second divide-by-2circuit B and outputs this signal to the divide-by-four unit UA. Thethird divide-by-2 circuit C is provided for proper loading.

The retiming unit RTU is provided in order to drive the phase selectingunit PSU and to control the phase switching by the control signals C0,C1, C2. The retiming unit RTU comprises a fourth and fifth divide-by-2circuit D, E and a swallow unit SU. The swallow unit determines how manypulses are to be swallowed.

The divide-by-4 unit UA comprises a sixth and seventh divide-by-2circuit F, G. The input of the sixth divide-by-2 circuit F is connectedto the output of the phase selection unit PSU and its In-phase outputsignals I_(p), I_(n) are connected to a load Ld, while its quadratureoutput Q_(p), Q_(n) is connected to the input of the seventh divide-by-2circuit. Finally, the In-phase output signals of the seventh divide-by-2circuit G constitutes the output of the 16/17 divider 10.

If no cycle-slip occurs, a total division of 16 can be achieved, sincein this case four divide-by-2 circuits A, B, F, G are connected inseries. Accordingly, if a cycle-slip occurs a division-by-17 can berealized with the divider 10.

The phase selecting unit PSU receives the four phase output signals ofthe second divide-by-2 circuit B as input signals. Since these signalsdiffer by 90° in phase with each other the following signals areprovided at the input of the phase selecting unit PSU: INi (0°, Ip), INq(90°, Qp), INni (180°, In) and INnq (270°, Qn). The phase selecting unitPSU selects one of the four input signals according to the three controlsignals C0, C1 and C2 as well as the inversions thereof.

If we assume that the output of the phase selecting unit PSU isinitially connected to INi, then the output will be connected to INqafter an raising edge of INi. Accordingly, the output of the phaseselecting unit PSU is delayed with ¼ T period of the input signals of aphase selecting unit PSU. However, since the input signals of the phaseselecting unit PSU have been divided by two divide-by-2 circuits, T willbe 4*To with To being the period of the input signal of the 16/17divider 10. As a result, one complete period To of the input signal isdelayed by the phase selection, i.e. a phase switching will result in adelay of one complete period of the input signal of the divider 10.

The waveforms Ip, Qp, In, Qn correspond to the phases 0°, 90°, 180°,270° of the second divide-by-2 circuit B, respectively, i.e. the periodT thereof equals 4*T0 the period of the input signal of the 16/17divider. As mentioned above, if a division-by-16 is to be realized bythe 16/17 divider, then no cycle-slip and no phase switching will occuri.e. the output of the PSU corresponds to a divide-by-4. However, if adivision-by-17 is to be realized, a phase switching will occur. Theswitching occurs in a fixed sequence and preferably in the sequence I,Q, nI, nQ, i.e. 0°, 90°, 180°, 270°. Therefore, if the input signal INi,i.e. I_(p), is initially connected to the output of the phase selectionunit PSU, then the input signal INq, i.e. Q_(p), will be selected andforms the output of the phase selection unit PSU. As soon as thisswitching occurs, an additional delay of 90°, which corresponds to aperiod of the input signal of the 16/17 divider, is introduced at theoutput of the PSU, i.e. the output of the PSU corresponds to adivide-by-5. In other words, the phase selection unit PSU introduces adelay or an extra cycle-slip to its input signal.

FIG. 4 shows a circuit diagram of a phase selecting unit PSU of FIG. 3.The circuit comprises 22 transistors T1-T22 and four resistors R. Thiscircuit is a particular implementation of the following logic code:OUT= NC0•NC1•Ini + NC0•C1•INni + C0•NC2•INnq + C0•C2•INq ,wherein +, •, represent an OR-, AND, and NAND functions, respectively.

OUT represents the output signal of the phase selecting unit PSU andINi, INni, INnq, INq represent the four input signals of a phaseselecting unit PSU. C0, C1 and C2 represent the control signals and NC0,NC1 and NC2 represent the inversions thereof. The signal C1 selectsbetween the input signals INi and INni, i.e. between 0 and 180°. Thesignal C2 selects between INq and INnq, i.e. between 90° and 270°. Theresult of the selection according to the control signal C1 is Pi and theresult of the selection of the control signal C2 is Pq. The controlsignal C0 selects between the results Pi and Pq. The input signal INi isinput to the transistor T17, the input signal INni to the transistorT18, the input signal INq to the transistor T20 and the input signalINnq to the transistor T19, respectively. In the next row oftransistors, i.e. T9-T16, the selection is performed according to thestates of C1, and C2, in order to achieve the selected signals Pi, Pq.The next row of transistors, i.e. T1-T8, is used to select one of thetwo selection signals Pi, Pq according to the state of the controlsignal C0.

The above logic code comprises four branches which are OR-connected. Thefirst branch is realized by the transistors T1, T9 and T17. The secondis implemented by the transistors T1, T11 and T18. The third branch isimplemented by transistors T3, T13 and T19. The fourth branch isimplemented by transistors T3, T15 and T20.

The AND logic function, e.g. the first branch NC0•NC1•INi, isimplemented differentially by current switching. The NAND logic isimplemented by differentially switching the inputs in the currentdomain. The OR logic is implemented by adding the output current of theNAND logic in the loads R. The advantage of such an implementation is anincreased speed due to the differential implementation in the currentdomain.

FIG. 5 shows a block diagram of the phase selecting unit PSU and theretiming unit RTU of FIG. 3. As mentioned above the retiming unit RTU isimplemented by a fourth and fifth divide-by-2 circuit D, E. The swallowunit SU is implemented by a D-latch DL. The D-latch DL receives theoutput ‘out’ of the 16/17 divider 10 as data input and a modulatorsignal ‘modul’ as clock input. The output signals Q, nQ of the D-latchDL are input to the fourth divide-by-2 circuit E, which provides fourphase output signals each differing in 90° in phase. The In-phase outputsignal Ip, In thereof constitutes the control signal C0, NC0. Thequadrature output Qp, Qn thereof is input to the fourth divide-by-2circuit D. The In-phase output signal Ip, In of the fourth divide-by-2circuit D constitutes the control signal C1, NC1 and the quadratureoutput signal Q_(p), Q_(n) constitutes the control signal C2, NC2. Asmentioned above, these three control signals C0, C1 and C2 are input tothe phase selecting unit PSU for controlling the phase selectiontherein. The modulator pulse represents the number of phase switchingwhich should occur. The signal ‘out’ represents the previous state ofthe phase selecting unit PSU, i.e. I, nI, Q, nQ. The phase switching isperformed in a fixed sequence, namely from I to Q, then to nI and to nQ,i.e. 0°, 90°, 180° and 270°. However, an alternative sequence is alsopossible.

FIG. 6 shows a timing diagram of the divider. The topmost waveform, i.e.VT(div_out) corresponds to the output of the divider. The lowest threewaveforms, i.e. VT(C0), VT(C1), VT(C2), correspond to the controlsignals C2, C1, C0, respectively. The waveform VT(mod_enable) correspondto the modulator input ‘modul’ of the D-latch DL of the retiming unitRTU. The waveform VT(out) corresponds to the output of the phaseselection unit PSU. The waveform VT(outl6) corresponds to the output ofthe seventh divide-by-2 circuit F, i.e. the output of the 16/17 divider10.

From the waveforms of the control signals C0, C1, C2 it can be seen thatthe waveform of C2 is 90° shifted with regards to the waveform of C1,since C1 and C2 correspond to the IN-phase and the quadrature phase ofthe output of the fourth divid-by-2 circuit D, respectively. The periodof the signals C1, C2 is twice as high as the period of the signal C0due to an additional divide-by-2 operation o the fourth divide-by-twocircuit D.

Summarizing it can be said, that rather than using a 4/5 divider as thebase, a single fixed 16/17-frequency-divider followed by a programmable5 stage integer-2 divider, i.e. controlled with 5 bits, was chosen. Theadvantage is that the block after the phase selector is now only needsto generate the signals /2, /4, /8, /16 and /32. In principle a 32/33divider can do the job in combination with a 4-stage integer-2 divider,however 32/33 (but also the 16/17 divider) operates at 5 GHz at theirinput which makes it hard to realize a 32/33-divider. A synchronizerincluding final D-flip-flop are needed to do time synchronization. Thesynchronizer and D-flip-flop generate the final output signal, i.e. theinput signal divided by any integer between 512 and 544 and realizes thesynchronization pulse to reclock the circuitry and remove delays due tothe latches.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.The word “comprising” does not exclude the presence of elements or stepsother than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.In the device claim enumerating several means, several of these meanscan be embodied by one and the same item of hardware. The mere fact thatcertain measures are recited in mutually different dependent claims doesnot indicate that a combination of these measures cannot be used toadvantage.

Furthermore, any reference signs in the claims shall not be construed aslimiting the scope of the claims.

1. Phase-switching dual modulus prescaler, comprising a dual modulusdivider (10) comprising: a first and second divide-by-2 circuit (A;B),wherein said second divide-by-2 circuit (B) is coupled to the output ofsaid first divide-by-2 circuit (A) and at least said seconddivide-by-two circuit (B) comprises four phase outputs (I_(p), I_(n),Q_(p), Q_(n); INi, IiNni, INq, INnq) each separated by 90°; a phaseselection unit (PSU) for selecting one of the four phase outputs (I_(p),I_(n), Q_(p), Q_(n); INi, INni, INq, INnq) of the second divide-by-2circuit (B); a phase control unit (RTU) for providing control signal(C1, NC0; C2, NC2; C3, NC3) to the phase selection unit (PSU), whereinthe phase selection unit (PSU) performs the selection of the four phaseoutputs (I_(p), I_(n), Q_(p), Q_(n); INi, INni, INq, INnq) according tothe control signals (C0, NC0; C1, NC1; C2, NC2); and said phaseselection unit (PSU) is implemented based on direct logic; wherein theoutput (OUT) of the phase selection unit (PSU) is implemented accordingto the following logic code:OUT= NC0•NC1•INi + NC0•C1•INni + C0•NC2•INnq + C0•C2•INq , +, •,represent an OR-, AND, and NAND functions, respectively.
 2. Prescaleraccording to claim 1, further comprising a divide-by-4 circuit (UA)coupled to the output of the phase selection unit (PSU), saiddivide-by-4 circuit (UA) comprises a sixth and seventh divide-by-2circuit (F,G) each with four phase outputs (I_(p), I_(n), Q_(p), Q_(n))separated by 90°, said seventh divide-by-2 circuit (G) being coupled tothe quadrature output (Q_(p), Q_(n)) of the sixth divide-by-2. 3.Prescaler according to claim 1, wherein the phase control unit (RTU)comprises a fourth and fifth divide-by-2 circuit (D, E) each with fourphase outputs (I_(p), I_(n), Q_(p), Q_(n)) separated by 90°, said fourthand fifth divide-by-2 circuit (D, E) being coupled in series, theIn-phase output signal (I_(p), I_(n)) of the fifth divide-by-2 circuit(E) corresponds to the control signal (C0), the In-phase output signal(I_(p), I_(n)) of the fourth divide-by-2 circuit (D) corresponds to thecontrol signal (C1), the quadrature phase output signal (Q_(p), Q_(n))of the fourth divide-by-2 circuit (E) corresponds to the control signal(C2).
 4. Prescaler according to claim 3, wherein the phase control unit(RTU) further comprises a D-latch (DL) coupled to the input of the fifthdivide-by-2 circuit (E), the D-latch (DL) receives the previous state ofthe In-phase output (I_(p), I_(n)) of the seventh divide-by-2 circuit(G) and a signal (modul) indicating the number of phase switching asinput signals.
 5. Prescaler according to claim 1, wherein said dualmodulus divider (10) is a 16/17 divider.
 6. Prescaler according to claim1, further comprising a synchronization loop coupled to the dual modulusdivider (10) for reclocking the dual modulus divider (10).
 7. Frequencysynthesizer comprising a prescaler according to claim
 1. 8.Phase-switching dual modulus prescaler, comprising a dual modulusdivider (10) comprising: a first and second divide-by-2 circuit (A;B),wherein said second divide-by-2 circuit (B) is coupled to the output ofsaid first divide-by-2 circuit (A) and at least said seconddivide-by-two circuit (B) comprises four phase outputs (I_(p), I_(n),Q_(p), Q_(n); INi INni, INq, INnq) each separated by 90°; a phaseselection unit (PSU) for selecting one of the four phase outputs (I_(p),I_(n), Q_(p), Q_(n); INi, INni, INq, INnq) of the second divide-by-2circuit (B); a phase control unit (RTU) for providing control signal(C1, NC0; C2, NC2; C3, NC3) to the phase selection unit (PSU), whereinthe phase selection unit (PSU) performs the selection of the four phaseoutputs (I_(p), I_(n), Q_(p), Q_(n); INi, INni, INq, INnq) according tothe control signals (C0, NC0; C1, NC1; C2, NC2); and said phaseselection unit (PSU) is implemented based on direct logic; wherein thephase control unit (RTU) comprises a fourth and fifth divide-by-2circuit (D, E) each with four phase outputs (I_(p), I_(n), Q_(p), Q_(n))separated by 90°, said fourth and fifth divide-by-2 circuit (D, E) beingcoupled in series, the In-phase output signal (I_(p), I_(n)) of thefifth divide-by-2 circuit (E) corresponds to the control signal (C0),the In-phase output signal (I_(p), I_(n)) of the fourth divide-by-2circuit (D) corresponds to the control signal (C1), the quadrature phaseoutput signal (Q_(p), Q_(n)) of the fourth divide-by-2 circuit (E)corresponds to the control signal (C2).
 9. Prescaler according to claim8, wherein the phase control unit (RTU) further comprises a D-latch (DL)coupled to the input of the fifth divide-by-2 circuit (E), the D-latch(DL) receives the previous state of the In-phase output (I_(p), I_(n))of the seventh divide-by-2 circuit (G) and a signal (modul) indicatingthe number of phase switching as input signals.
 10. Prescaler accordingto claim 8, wherein said dual modulus divider (10) is a 16/17 divider.11. Prescaler according to claim 8, further comprising a synchronizationloop coupled to the dual modulus divider (10) for reclocking the dualmodulus divider (10).
 12. Frequency synthesizer comprising a prescaleraccording to claim 8.